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Silicon

VLSI & Digital Design

Twelve weeks of RTL. You specify, code, verify and synthesise a digital block, then present timing and area results the way a design review expects.

Curriculum

  1. Week 1

    Digital foundations

    Combinational and sequential logic, FSMs.

  2. Week 2

    Verilog RTL

    Coding style, synthesisable constructs, pitfalls.

  3. Week 3

    Verification

    Testbenches, assertions and coverage.

  4. Week 4

    Project build

    Design and synthesise your own block.

What you walk away with

  • A synthesised RTL block with a testbench
  • Timing, area and power analysis
  • A design review presentation

How the stipend works for VLSI & Digital Design

Verification coverage is a graded component. Score 90+ and you receive the full ₹8,000.

  • 01

    Curriculum Completion (20 pts)

    Finish all lessons and pass the module checkpoints.

  • 02

    Project Quality (60 pts)

    Graded by your mentor on craft, correctness and clarity.

  • 03

    Engagement (20 pts)

    Live Q&A attendance and peer reviews inside your cohort.

Your score, your payout

  • 90–100100% of max stipend₹8,000
  • 75–8970% of max stipend₹5,600
  • 60–7440% of max stipend₹3,200
  • Below 60Not yet eligible — resubmit to improve